Jun 24, 2021 10:52 AM (GMT+8) · EqualOcean
The first risc-v China Summit was held in Shanghai University of science and technology this week. This is the first time that risc-v has held a summit of the same scale outside North America. At this conference, Bao Yungang, Professor of the University of Chinese Academy of Sciences and researcher of the Institute of computing of Chinese Academy of Sciences, announced the core of domestic open source high-performance risc-v processor Xiangshan. Its core is named after "Lake", and its architecture code is "Yanqi Lake". The first generation is called "Yanqi Lake". The RTL code of "Yanqi Lake" was completed in April this year, and it is planned to be streamed based on TSMC 28nm process in July. The second generation architecture, called "Nanhu", will adopt SMIC 14nm technology and is expected to be rolled out by the end of this year. Beijing micronucleus chip participated in the first phase of the design work. At present, the team is recruiting partners for Xiangshan processor phase II joint development, and the companies that have joined are byte beat and other companies.

This text is a result of machine translation.